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AKTU VLSI Circuit Testing and Testability (BVL603) Syllabus PDF – B.Tech 3rd Year
VLSI Circuit Testing and Testability BVL603
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Official AKTU syllabus of VLSI Circuit Testing and Testability (BVL603) for B.Tech 3rd Year – 4 credits, L-T-P 3-1-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — VLSI Circuit Testing and Testability
Download PDFBVL603 · 4 credits · L-T-P 3-1-0
| Unit | Topics | Lectures |
|---|---|---|
| I | Faults in Digital Circuits: Fault modelling, fault detection, redundancy, equivalence, fault location, fault dominance. Stuck at faults, bridging faults, stuck open faults, Transient faults, Permanent faults. | 8 |
| II | Testing and Testability of Combinational Circuits Test generation basics, test generation algorithms, path sensitization, Boolean difference, D-algorithm, PODEM, Testable combinational logic circuit design. | 8 |
| III | Testing and Testability of Sequential Circuits Testing of sequential circuits as iterative combinational circuits, State table verification, Test generation based on circuit structure, Design of testable sequential circuits, Ad Hoc design rules, Scan path technique (scan design), Partial scan, Boundary scan | 8 |
| IV | Memory, Delay, Fault AND IDDQ Testing Testable memory design, RAM fault models, test algorithms for RAMs, Delay faults, Delay test, IDDQ testing, limitations of IDDQ Testing | 8 |
| V | Design for testability: controllability and observability, Random test generation, transition count testing, signature analysis, syndrome testable design, RMC, Level sensitive scans design, BIST: LSSD on-chip self-test, BILBO, BIDCO. | 8 |
Text Books
- P. K. Lala, “Digital Circuit Testing and Testability”, Academic Press.
- M.L. Bushnell and V.D. Agrawal, “Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits”, Kluwar Academic Publishers.
Reference Books
- N.K. Jha and S.G. Gupta, “Testing of Digital Systems”, Cambridge University Press.
- Zainalabe Navabi, “Digital System Test and Testable Design: Using HDL Models and Architectures”, Springer.
Course Outcomes
- Understand the concepts of digital testing and Fault models.
- Apply fault equivalence and dominance collapsing.
- Apply fault simulation algorithms on digital circuits.
- Understand and analyze combinational ATPG algorithms.
- Design testable combinational & sequential circuits.
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