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AKTU CAD (computer-Aided Design) for Electronics Lab (BEC653B) Syllabus PDF – B.Tech 3rd Year

CAD (computer-Aided Design) for Electronics Lab BEC653B

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  • Semester 6
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Official AKTU syllabus of CAD (computer-Aided Design) for Electronics Lab (BEC653B) for B.Tech 3rd Year – 1 credits, L-T-P 0-0-2. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.

Syllabus — CAD (computer-Aided Design) for Electronics Lab

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BEC653B · 1 credits · L-T-P 0-0-2

List of Experiments

Part A PSPICE Experiments:

  1. (a) Transient Analysis of BJT inverter using step input. (b) DC Analysis (VTC) of BJT inverter
  2. (a) Transient Analysis of NMOS inverter using step input.
  • Transient Analysis of NMOS inverter using pulse input.
  • DC Analysis (VTC) of NMOS inverter.
  1. (a) Analysis of CMOS inverter using step input.
  • Transient Analysis of CMOS inverter using step input with parameters.
  • Transient Analysis of CMOS inverter using pulse input.
  • Transient Analysis of CMOS inverter using pulse input with parameters.
  • DC Analysis (VTC) of CMOS inverter with and without parameters.
  1. Transient & DC Analysis of NAND Gate using CMOS inverter.
  2. Transient Analysis of NOR Gate inverter and implementation of XOR gate using NOR gate
  3. To design and perform transient analysis of D latch using CMOS inverter.
  4. To design and perform the transient analysis of SR latch circuit using CMOS inverter.
  5. To design and perform the transient analysis of CMOS transmission gate.
  6. Analysis of frequency response of Common Source amplifiers.
  7. Analysis of frequency response of Source Follower amplifiers Part B : HDL (using VHDL program module & verilog Module) VHDL PROGRAMS
  8. Design and Simulation of Full Adder using VHDL program module
  9. Design and Simulation of 4x1 MUX using VHDL program module
  10. Design and Simulation of BCD to Excess-3 code using VHDL program module
  11. Design and Simulation of 3 to 8 decoder using VHDL program module
  12. Design and Simulation of JK Flip-flop using VHDL program module
  13. Design and Simulation of CMOS Inverter using verilog Module

Course Outcomes

  1. Design and analyze the performance of different type of inverters.
  2. Design and analyze the performance of the basic logic gates using CMOS inverter circuit.
  3. Design and analyze the performance of the memory based digital circuits using CMOS inverter circuit.
  4. Analyze the performance of the different configuration of MOS amplifier circuits.

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