AKTU Physical Design for VLSI Circuits Lab (BVL652) Syllabus PDF – B.Tech 3rd Year

List of Experiments

1. Perform RTL synthesis to generate a gate-level netlist from Verilog or VHDL code.
2. Make Floorplan of a Digital Design Block
3. Carry out standard cell and macro placement to optimize area and performance.
4. Power Planning: Creation of Power Rings and Straps
5. Design and analyze a clock tree structure to minimize skew and meet timing constraints.
6. Perform global and detailed routing to complete interconnections between placed cells.
7. Perform static timing analysis to verify setup and hold timing violations.
8. Parasitic Extraction and RC Delay Estimation
9. Conduct Design Rule Check (DRC) and Layout Versus Schematic (LVS) Verification.
10. Generate the final GDSII file for fabrication-ready layout submission. Content beyond the Course: Experiments related to RTL synthesis, floorplanning, standard cell placement, power planning, clock tree synthesis (CTS), global and detailed routing, static timing analysis (STA), parasitic extraction, RC delay estimation, Design Rule Check (DRC), Layout Versus Schematic (LVS) verification, and GDSII generation, as covered in this suggestive list, can be implemented and verified using “Siemens EDA (Calibre)/ Cadence/ Synopsys or similar relevant software tools”.

Course Outcomes

1. Apply physical design concepts to synthesize RTL code into a gate-level netlist.
2. Perform floor planning, placement, and power planning for digital integrated circuits.
3. Implement clock tree synthesis and routing while analyzing clock skew and congestion.
4. Evaluate the timing, power, and parasitic effects in VLSI layouts through STA and extraction techniques.
5. Validate physical designs through DRC, LVS, and generate final GDSII layouts for fabrication readiness.