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AKTU Analog Integrated Circuit Design (BVL053) Syllabus PDF – B.Tech 3rd Year
Analog Integrated Circuit Design BVL053
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Official AKTU syllabus of Analog Integrated Circuit Design (BVL053) for B.Tech 3rd Year – 3 credits, L-T-P 3-0-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — Analog Integrated Circuit Design
Download PDFBVL053 · 3 credits · L-T-P 3-0-0
| Unit | Topics | Lectures |
|---|---|---|
| I | Introduction to System Design and Verification • Fundamentals of System Design: Introduction to system-on-chip (SoC) and embedded system design, Hardware/software co-design principles, Model-based design and virtual prototyping. • Verification Challenges and Methodologies: Importance of verification in digital system design, Directed vs. constrained-random verification, Coverage-driven verification (functional, code, FSM, toggle coverage). | 8 |
| II | Introduction to Full Custom IC Design Flow, Siemens/Cadence/Synopsys Solutions for Custom IC Design, MOSFET Characterization, Schematic Capture using SiemensSolid S- Edit/ Virtuoso Schematic Editor/ Synopsys Custom Compiler, Symbol Creation. Testbench Creation using SiemensSolido Design Environment/ Cadence Virtuoso ADE/Synopsys PrimeWave, Functional Simulation using Analog FastSPICE/ Cadence Spectre, or Synopsys HSPICE, Delay Estimation, Power estimation, Monte-Carlo. | 8 |
| III | Introduction to IC Physical Design Flow, Physical Design (PD) Flow tools (Siemens EDA – Aprisa/ Cadence – Innovus/ Synopsys – IC Compiler II), Functional Simulation using Siemens QuestaSim/ Cadence Xcelium/ Synopsys VCS, Coverage Analysis using Siemens QuestaSim/Questa Verification IQ/Cadence Verisium/Synopsys VCS Verdi, Introduction to TCL Scripting, RTL Synthesis using Siemens Precision RTL/Cadence Genus/Synopsys Design Compiler. | 8 |
| IV | Layout Design using Siemens EDA L-Edit/ Cadence Virtuoso Layout Suite/Synopsys Custom Compiler, Physical Verification including DRC and LVS using Siemens Calibre/Cadence Pegasus/Synopsys IC Validator (ICV), Parasitic Extraction using Siemens CalibrexACT/CalibrexRC, Cadence Quantus/ Synopsys StarRC, Post-Layout Simulation using Siemens Analog FastSPICE (AFS)/ Cadence Spectre/Synopsys HSPICE, and Generation of GDSII. | 8 |
| V | Physical Implementation using Siemens EDA Aprisa / Cadence Innovus / Synopsys IC Compiler II (ICC2), including Floor Planning, Power Planning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Analysis, Power Analysis, Parasitic Extraction, Generation of GDSII. | 8 |
Note: As mentioned above any ONE of the three EDA tools may be made use of depending upon the availability. The questions asked in exam will not be from any specific EDA tool and will be of generic nature.
Text Books
- System Verilog for Verification: A Guide to Learning the Testbench Language Features, Chris Spear & Greg Tumbush, Springer, 2nd Edition, 2012.
- N.A.Sherwani, "Algorithms for VLSI Physical Design Automation", (3/e), Kluwer, 1999.
- CMOS: Circuit Design, Layout, and Simulation, R. Jacob Baker, Wiley-IEEE, 3rd Edition, 2010.
Reference Books
- UVM Primer: A Step-by-Step Introduction to the Universal Verification Methodology, Mark Glasser, Boston Light Press, 2014.
- The Complete Formal Verification Guide, SasanIman&Sunita Joshi – Synopsys Press, 2004.
- Andrew B. Kahng, Jens Lienig, Igor L. Markov, JinHu, VLSI Physical Design: From Graph Partitioning to Timing Closure, Springer, 2011.
Course Outcomes
- Understand system-level design methodologies and their role in IC design.
- Develop and simulate custom IC schematics using Cadence Virtuoso.
- Perform functional verification and analyze coverage using Incisive and IMC tools.
- Implement IC physical design flow, including synthesis, layout design, and parasitic extraction.
- Implement physical implementation steps, including floor planning, power planning, placement, routing, and GDSII generation.
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