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AKTU Digital Design with FPGA Lab (BVL651) Syllabus PDF – B.Tech 3rd Year
Digital Design with FPGA Lab BVL651
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Official AKTU syllabus of Digital Design with FPGA Lab (BVL651) for B.Tech 3rd Year – 1 credits, L-T-P 0-0-2. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — Digital Design with FPGA Lab
Download PDFBVL651 · 1 credits · L-T-P 0-0-2
List of Experiments
- Simulate all gates using VHDL.
- Design and simulate Half adder and Full adder using VHDL.
- Design and simulate Multiplexer and Demultiplexer using VHDL.
- Design and simulate Encoder and Decoder using VHDL.
- Simulate Flip flops using VHDL.
- Implement shift register using VHDL.
- FPGA implementation of Flip flops.
- FPGA implementation of shift register.
- Design and implement 4-bit Synchronous and Asynchronous Counters on FPGA
- Implement Binary Multiplier using FPGA
Course Outcomes
- Design and simulate basic logic gates and arithmetic circuits using VHDL.
- Design and simulate multiplexers, encoders, and decoders using VHDL.
- Implement sequential logic circuits such as flip-flops and shift registers using VHDL.
- Implement and test sequential and arithmetic circuits on FPGA hardware.
- Demonstrate the ability to integrate and debug VHDL code in FPGA-based digital design workflows.
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