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AKTU CMOS Digital Design Techniques (BEC063) Syllabus PDF – B.Tech 3rd Year
CMOS Digital Design Techniques BEC063
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Official AKTU syllabus of CMOS Digital Design Techniques (BEC063) for B.Tech 3rd Year – 3 credits, L-T-P 3-0-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — CMOS Digital Design Techniques
Download PDFBEC063 · 3 credits · L-T-P 3-0-0
| Unit | Topics | Lectures |
|---|---|---|
| I | VLSI design flow, VLSI design style, introduction to the basic fabrication processes (wafer preparation, oxidation, diffusion, etching, metallization and lithography, etc.), Fabrication process Flow: basic Steps, the CMOS n-well Process. Metal oxide semiconductor (MOS) structure, Types of MOSFET: Enhancement and Depletion. Structure and operation of MOS transistor. | 8 |
| II | Threshold voltage equation and energy band diagram of MOSFET, controlling of threshold voltage, MOSFET current – Voltage Characteristics. Transconductance, Drain conduction. Aspect ratio, process parameters, second order effects, MOS small signal and Large signal model, MOS capacitances. Stick diagram rules for nMOS and CMOS technology, lambda based and micron-based design rules. Layout design for CMOS inverter | 8 |
| III | Analysis of different types of inverter circuit, CMOS inverter, transfer characteristic, calculation of propagation delay, rise time, fall time, noise margin and power dissipation for CMOS Inverter. Effect of threshold voltage and supply voltage on Delay and power dissipation. Limitations of CMOS in NANO scale circuit design. | 8 |
| IV | CMOS logic, Complex Logic Circuits, pseudo NMOS logic, pass transistor logic, Transmission Gate logic and Dynamic logic circuit design. Designing of Combinational logic circuit using CMOS and analysis of various design parameters. | 8 |
| V | Sequential MOS Logic circuits, SR Latched circuits, clocked latch and Flip Flop Circuits, CMOS D latch and Edge Triggered Flip Flop, Design of the Schmitt trigger circuit, Dynamic random access and Static random access memory cell design and analysis, Sense amplifier and row and column decoder circuit. | 8 |
Text Books
- Sung-mo Kang and Yusuf Leblebici, CMOS Digital Integrated Circuit analysis and Design, Tata McGraw-Hill, 3/e.
- R. Jacob Baker, Harry W. Li and David E. Boyce, CMOS Circuit design, layout and Simulation, PHI, IEEE press, Series Edition,
Reference Books
- Yuan Taur and Tak H. Ning, Fundamentals of Modern VLSI Devices, Cambridge university Press, Special Edition, 1998
- Neil H.E. Weste and Kamran Esharhian, Principal of CMOS VLSI design, PHI, 2/e
- Jan M. Rabaey, Digital Integrated Circuit, PHI, 2/e
Course Outcomes
- Understand the static and dynamic behavior of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) and the secondary effects of the MOS transistor model.
- To be aware about the trends in semiconductor technology, and how it impacts scaling and its effect on device density, speed and power consumption.
- To understand MOS transistor as a switch and its capacitance.
- Student will be able to design digital systems using MOS circuits (Static and Switching characteristics of inverters)
- Understand the concept behind ASIC (Application Specific Integrated Circuits) design and the different implementation approaches used in industry.
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