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AKTU Digital Integrated Circuit Design (BVL051) Syllabus PDF – B.Tech 3rd Year
Digital Integrated Circuit Design BVL051
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Official AKTU syllabus of Digital Integrated Circuit Design (BVL051) for B.Tech 3rd Year – 3 credits, L-T-P 3-0-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — Digital Integrated Circuit Design
Download PDFBVL051 · 3 credits · L-T-P 3-0-0
| Unit | Topic | Lectures |
|---|---|---|
| I | Fundamentals of Synthesis and Digital Design Flow: Introduction to ASIC and FPGA Design Flow: RTL-to-GDSII flow, Role of synthesis in digital design Basics of Hardware Description Languages (HDLs): System Verilog vs. VHDL for synthesis, RTL coding guidelinesandstyles for efficient synthesis. Introduction to Pre-Synthesis Analysis and RTL Quality Checks using Lint, CDC, RDC, and Formal Verification technologies such as Siemens Questa SFV, Cadence JasperGold and Verisium, Synopsys VC Formal and SpyGlass, etc. | 8 |
| II | Introduction to Logic Synthesis: Definition and purpose of synthesis, technology-independent vs. technology-dependent optimizations, synthesis tools overview (Siemens EDA – Precision RTL/Aprisa, Cadence – Genus/Innovus, Synopsys – Design Compiler/IC Compiler II), etc. | 8 |
| III | Static Timing Analysis (STA) Basics: Fundamentals of Timing Analysis: Setup time, hold time, propagation delay, Clock period, clock skew, and clock jitter. | 8 |
| IV | Timing Paths: Types of Timing Paths in a Digital Circuit: Data path, clock path, asynchronous paths, Critical path analysis. Timing Models and STA Basics: Transition time, cell delay, net delay, Wire-load models, parasitic extraction. | 8 |
| V | Introduction to Static Timing Analysis (STA), Introduction to Gate-Level Simulation (GLS) and verification, understanding Standard Delay Format (SDF), GLS using Siemens QuestaSim, Cadence Xcelium, or Synopsys VCS, Functional Verification using Siemens Questa Formal/Questa SFV, Cadence JasperGold, or Synopsys VC Formal, Pre- and Post-Synthesis Analysis, and Introduction to Power Analysis using Siemens PowerPro, Cadence Joules, or Synopsys PrimePower. | 8 |
Note: As mentioned above any ONE of the three EDA tools may be made use of depending upon the availability. The questions asked in exam will not be from any specific EDA tool and will be of generic nature.
Text Books
- Digital Integrated Circuit Design: From VLSI Architectures to CMOS Fabrication, Hubert Kaeslin, Cambridge University Press, 2008.
- Verilog HDL: A Guide to Digital Design and Synthesis, Samir Palnitkar, Pearson, 2nd Edition, 2003.
Reference Books
- Introduction to VLSI Design Flow, SnehSaurabh, Cambridge University Press 2023.
- The Designer's Guide to VHDL, Peter J. Ashenden, Morgan Kaufmann, 3rd Edition, 2008. COURSE OUTCOME: After completion of the course, student will be able to:
- Explain the digital design flow, including RTL-to-GDSII, and the importance of synthesis in ASIC/FPGA design.
- Write efficient RTL code in Verilog/VHDL and apply synthesis optimizations.
- Perform Static Timing Analysis (STA) by understanding timing parameters and constraints.
- Apply functional verification methods and use tools such as Conformal LEC for equivalence checking.
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