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AKTU Advanced Digital Design Using Verilog (BECZ052) Syllabus PDF – B.Tech 3rd Year
Advanced Digital Design Using Verilog BECZ052
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Official AKTU syllabus of Advanced Digital Design Using Verilog (BECZ052) for B.Tech 3rd Year – 3 credits, L-T-P 3-0-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — Advanced Digital Design Using Verilog
Download PDFBECZ052 · 3 credits · L-T-P 3-0-0
Course Outcomes
At the end of course, the student will be able to:
| CO 1 | Describe mixed logic circuits and their implementation. | K K 1, 2 |
| CO 2 | Implement combinational circuits using mixed logic and Verilog. | K , K 4 5 |
| CO 3 | Design sequential circuits using mixed logic and Verilog with mapping of Algorithm. | K , K 2 3 |
| CO 4 | Understand faults and its elimination in sequential and combinational circuits. | K , K 1 2 |
| CO 5 | Understand the working of programmable logic families. | K , K 1 2 |
Course Content
L-T-P: 3-0-0
| Unit | Topic | Proposed Lecture |
|---|---|---|
| I | Introduction to Mixed Logic, Logic Representation and Minimization with cost, Multiple output minimization, Entered Variable K- Map including don’t care handling, XOR Pattern Handling. | 08 |
| II | Combinational Circuit Design, Multiplexers, Decoders, Encoders, Code Comparators, Adders, Subtractors, Multipliers, Introduction to Verilog, Behavioral and Structural specification of logic circuits, Boolean function implementation using Verilog, Timing Analysis, Hazard Detection and Elimination | 08 |
| III | Synchronous Sequential Circuits Design, Mapping Algorithm, Synchronous State Machines, ASM Charts, Asynchronous Sequential Circuit Design, Races, Multi-level minimization and optimization. | 08 |
| IV | Factoring, Decomposition, BDD, Ordered BDD, LPDD, Fault Detection and Analysis in combinational and sequential systems, Path Sensitization method, Boolean Difference Method, Initial State Method. | 08 |
| V | Study of programmable logic families, PLD, CPLD, FPGA, ASIC, PLA, Architectures, Design of Combinational and sequential circuits using CPLD and FPGA, Design Examples. | 08 |
Text Books
- Richard F. Tinder, “Engineering Digital Design”, Academic Press.
- Parag K. Lala, “Digital system Design Using PLDs”, PHI India Ltd.
- Stephen Brown and ZvonkoVranesiv, “Fundamental of Digital Logic with Verilog Design”, McGraw Hill.
Reference Books
- John Williams, “Digital VLSI Design with Verilog”, Springer Publication..
- Samuel C. Lee, “Digital Circuit and Logic Design”, PHI India Ltd.
- Alexander Miczo, “Digital Logic Testing and Simulation”,Wiley Interscience.
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