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AKTU VLSI Design Flow: RTL to GDS (BEC078) Syllabus PDF – B.Tech 4th Year
VLSI Design Flow: RTL to GDS BEC078
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Official AKTU syllabus of VLSI Design Flow: RTL to GDS (BEC078) for B.Tech 4th Year – 3 credits, L-T-P 3-0-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — VLSI Design Flow: RTL to GDS
Download PDFBEC078 · 3 credits · L-T-P 3-0-0
| Unit | Topics | Lectures |
|---|---|---|
| I | Fundamentals of VLSI Design Flow and HDL Basic concept of Integrated Circuits, Moore’s law, Scales of Integration, Introduction to ASIC and SoC design, VLSI Design flow, FPGA Design Flow, Technology nodes, GDSII file format definition, PDK definition, Introduction to EDA tools used in front-end and back-end design. VLSI Design Styles Basics of Hardware Description Languages (HDLs): Verilog HDL fundamentals, modeling styles – Dataflow, Behavioral and Structural modeling. Module definition, ports, data types and operators in verilog. | 10 |
| II | RTL Design and Functional Verification Blocking vs Non-blocking assignments, Always blocks-combinational & sequential modeling, Control blocks: if-else, case and loops. RTL implementation of combinational and sequential circuits. FSM design (Moore & Mealy). Functional simulation and test benches development. Introduction to simulation tools (e.g., Xcelium) and waveform analysis. | 8 |
| III | Logic Synthesis and Static Timing Analysis Logic synthesis flow: RTL to gate-level netlist. Technology mapping and synthesis constraints (introduction to SDC). Inputs and outputs of synthesis, Gate-level netlist generation and analysis. Overview of synthesis optimization (timing, area and power – introductory). Synthesis tools overview. Static Timing Analysis (STA): Propagation delay, clock skew, and clock jitter. Setup and hold check. Timing paths, slacks and timing reports. | 7 |
| IV | Introduction to Physical Design Overview of Physical Design flow. Floorplanning concepts and partitioning (basic). Placement of standard cells and macros (overview). Clock Tree Synthesis (CTS) – concept and objectives. Routing – global and detailed routing (introductory). Power planning basics (power rings, power stripes). Congestion analysis (basic understanding). | 7 |
| V | Physical Verification and Signoff Design Rule Checking (DRC) – purpose and methodology. Layout vs Schematic (LVS), Parasitic extraction (RC extraction overview), Introduction to Signal integrity and IR drop concepts, Tape-out procedure and GDSII generation. | 8 |
Text Books
- Sneh Saurabh, Introduction to VLSI Design Flow, McGraw Hill Education (India), 1st Edition, 2018.
- Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Pearson Education, 2nd Edition, 2003.
- Naveed A. Sherwani, Algorithms for VLSI Physical Design Automation, Springer, 3rd Edition, 1999.
Reference Books
- Michael D. Ciletti, Advanced Digital Design with the Verilog HDL, Pearson Education, 2nd Edition, 2011.
- Khosrow Golshan, Physical Design Essentials: An ASIC Design Implementation Perspective, Springer, 1st Edition, 2007.
- S. K. Lim, Practical Problems in VLSI Physical Design Automation, Springer, 1st Edition, 2013.
Course Outcomes
- Explain the complete VLSI design flow from specification to tape-out.
- Design and simulate RTL modules using Verilog HDL.
- Perform logic synthesis and analyze timing, area, and power reports.
- Explain basic physical design stages including floor planning, placement, CTS and routing.
- Perform physical verification and interpret signoff result.
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