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AKTU ASIC Design and Verification (BEC076) Syllabus PDF – B.Tech 4th Year
ASIC Design and Verification BEC076
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Official AKTU syllabus of ASIC Design and Verification (BEC076) for B.Tech 4th Year – 3 credits, L-T-P 3-0-0. Read the unit-wise course content, course outcomes, evaluation pattern and recommended books online, or download the PDF.
Syllabus — ASIC Design and Verification
Download PDFBEC076 · 3 credits · L-T-P 3-0-0
| Unit | Topics | Lectures |
|---|---|---|
| I | ASIC Design Flow and System Verilog Fundamentals Overview of ASIC design flow, Role of RTL and Verification in ASIC design. SystemVerilog overview and evolution from Verilog. Data Types: logic, bit, reg, wire, Constants, Net Type, Arrays: static, dynamic, associative, queues, Enumerated types, Typedef and packages, String, Operators and expressions. Procedural statements and Routines - Procedural Statements, Specialized constructs: always_comb, always_ff, always_latch. Tasks, Functions, and Void Functions, Routine arguments – Returning from a routine. | 8 |
| II | Combinational Circuit Modeling using SystemVerilog Continuous assignments. Sensitivity lists and always_comb., Blocking assignment, Modeling and verification of-Multiplexer, Encoder / Decoder, Adder / Subtractor, Comparator, Parameterized combinational modules | 8 |
| III | Sequential Circuit Modeling using SystemVerilog always_ff construct, non-blocking assignment, Modeling and verification of- Flip-flops, Counters (Up/Down, Mod-N), Shift registers, FSM design (Moore & Mealy). Clock and reset strategies (synchronous/asynchronous). | 8 |
| IV | Verification Fundamentals Need for verification, Testing Vs Verification, Separation of Testbench and Design, Testbench architecture. Interface Construct, Stimulus Timing, Module interactions. Direct Testing. Self-checking testbench. Scoreboard concept. System Verilog Assertions, Procedural and Concurrent Assertions. | 8 |
| V | Digital Design using FPGA FPGA Design flow, Applications of FPGA, FPGA Architecture, Introduction to FPGA development environments (Vivado Tool), FPGA implementation of combinational circuits: logic gates, adder, subtractor, decoder, multiplexer. FPGA implementation of sequential circuits: Flip flops and counter with & without inclusion of constraint file. | 8 |
Text Books
- Christian B Spear, “System Verilog for Verification: A guide to learning the Testbench language features”, Springer publications, Third Edition, 2012.
- Stuart Sutherland, Simon Davidmann and Peter Flake, SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling, Springer, 2nd Edition, 2006.
- Z. Navabi, Digital System Design with FPGA: Implementation Using Verilog and VHDL, Springer International Publishing, 2018.
Reference Books
- Ashok B. Mehta, Introduction to SystemVerilog, Springer, 2nd Edition, 2021.
- Sanjay Churiwala, Usha Mehta and Vaishali Dhare, Digital Design and Verification using Verilog and SystemVerilog, Wiley India, 2024.
- Mark Zwoliński, Digital System Design with SystemVerilog, Prentice Hall Modern Semiconductor Design, 2010/2016.
- Janick Bergeron, Writing Testbenches using SystemVerilog, Synopsys Inc., Springer Publications, 2006.
Course Outcomes
- Understand ASIC design flow and SystemVerilog fundamentals.
- Apply SystemVerilog constructs to implement combinational circuits.
- Apply SystemVerilog constructs to implement sequential circuits.
- Analyze structured testbenches using assertions and coverage techniques.
- Construct Digital Circuits on FPGA platform.
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